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Hi-performance Regulator IC Series for PCs
Main Power Supply ICs for Note PC (Linear Regulator Integrated)
BD9528MUV
No.10030EAT26
Description BD9528MUV is a 2ch switching regulator controller with high output current which can achieve low output voltage (1.0V 5.5V) from a wide input voltage range (5.5V28V). High efficiency for the switching regulator can be realized by utilizing an external N-MOSFET power transistor. A new technology called H3RegTM(High speed, High efficiency, High performance) is a Rohm proprietary control method to realize ultra high transient response against load change. SLLM (Simple Light Load Mode) technology is also integrated to improve efficiency in light load mode, providing high efficiency over a wide load range. For protection and ease of use, 2ch LDO (5V/100mA, 3.3V/100mA), the soft start function, variable frequency function, short circuit protection function with timer latch, over voltage protection, and Power good function are all built in. This switching regulator is specially designed for Main Power Supply of laptop PC. Features 1) 2ch H3REGTM DC/DC Converter controller 2) Adjustable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and Forced continuous Mode 3) Thermal Shut Down (TSD), Under Voltage LockOut (UVLO), Over Current Protection (OCP), Over Voltage Protection (OVP), Short circuit protection with 0.75ms timer-latch (SCP) 4) Soft start function to minimize rush current during startup 5) Switching Frequency Variable (f=200kHz500kHz) 6) Built-in Power good circuit 7) Built-in 2ch Linear regulator (5V/100mA,3.3V/100mA) 8) Built in reference voltage(0.7V) 9) VQFN032V5050 package 10) Built-in BOOT-Di 11) Built-in output discharge
Applications Laptop PC, Desktop PC, LCD-TV, Digital Components
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Absolute maximum ratings (Ta=25) Parameter Symbol VIN, CTL,SW1,SW2 EN1, EN2, PGOOD1, PGOOD2 Vo1, Vo2, MCTL1, MCTL2 FS1, FS2, FB1, FB2, ILIM1, ILIM2, SS1, SS2, LG1, LG2, REF,REG2 BOOT1, BOOT2 BOOT1-SW1, BOOT2-SW2, HG1-SW1, HG2-SW2 HG1 HG2 PGND1, PGND2 Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax Limits 30 *1*2 6 *1*2 REG1+0.3 *1 35 *1*2 7 *1*2 BOOT1+0.3 *1*2 BOOT2+0.3 *1*2 AGND0.3 *1*2 0.38 *3 0.88 *4 3.26 *5 6 4.56 * -20+100 -55+150 +150
Technical Note
Unit V V V V V V V V W W W W
Terminal Voltage
Power Dissipation1 Power Dissipation2 Power Dissipation3 Power Dissipation4 Operating temperature Range Storage temperature Range Junction Temperature
*1 Do not however exceed Pd. *2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 Reduced by 3.0mW for each increase in Ta of 1 over 25 (when don't mounted on a heat radiation board ) *4 Reduced by 7.0mW for increase in Ta of 1 over 25. (when mounted on a board 74.2mmx74.2mmx1.6mm Glass-epoxy PCB which has 1 layer. (Copper foil area : 20.2mm2) *5 Reduced by 26.1mW for increase in Ta of 1 over 25. (when mounted on a board 74.2mmx74.2mmx1.6mm Glass-epoxy PCB which has 4 layers. (1st and 4th copper foil area : 20.2mm2, 2nd and 3rd copper foil area : 5505mm2) *6 Reduced by 36.5mW for increase in Ta of 1 over 25. (when mounted on a board 74.2mmx74.2mmx1.6mm Glass-epoxy PCB which has 4 layers. (All copper foil area : 5505mm2)
Operating conditions(Ta=25) Parameter Symbol VIN CTL EN1, EN2, MCTL1, MCTL2 BOOT1, BOOT2 SW1, SW2 BOOT1-SW1, BOOT2-SW2, HG1-SW1, HG2-SW2 Vo1, Vo2, PGOOD1, PGOOD2 TONmin MIN. 5.5 -0.3 -0.3 4.5 -0.3 -0.3 -0.3 MAX. 28 28 5.5 33 28 5.5 5.5 150 Unit V V V V V V V nsec
Terminal Voltage
MIN ON TIME
This product should not be used in a radioactive environment.
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Electrical characteristics (unless otherwise noted, Ta=25 VIN=12V, CTL=OPEN, EN1=EN2=5V, FS1=FS2=51k) Standard Value Parameter VIN standby current VIN bias current VIN shut down mode current CTL Low Voltage CTL High Voltage CTL bias current EN Low Voltage EN High Voltage EN bias current [5V linear regulator](VIN) REG1 output voltage Maximum current Line Regulation Load Regulation [3.3V linear regulator] REG2 output voltage Maximum current Line Regulation Load Regulation [5V linear regulator](Vo1) Input threshold voltage Input delay time Switch resistance [Under Voltage lock out block] REG1 threshold voltage Hysteresis voltage [Output voltage sense block] Feedback voltage1 FB1 bias current Output discharge resistance1 Feedback voltage2 FB2 bias current Output discharge resistance2 VFB1 IFB1 RDISOUT1 VFB2 IFB2 RDISOUT2 0.693 50 0.693 50 0.700 0 100 0.700 0 100 0.707 1 200 0.707 1 200 V A V A REG1_UVLO dV_UVLO 3.9 50 4.2 100 4.5 200 V mV REG1th TREG1 RREG1 4.1 1.5 4.4 3.0 1.0 4.7 6.0 3.0 V ms VREG2 IREG2 Reg.l2 Reg.L2 3.27 100 3.30 3.33 20 30 V mA mV mV VREG1 IREG1 Reg.l1 Reg.L1 4.90 100 5.00 90 30 5.10 180 50 V mA mV mV Symbol MIN. ISTB IIN ISHD VCTLL VCTLH ICTL VENL VENH IEN 70 60 6 -0.3 2.3 -18 -0.3 2.3 TYP. 150 130 12 -12 3 MAX. 250 230 18 0.8 28 -6 0.8 5.5 6 A A A V V A V V A Unit
Technical Note
Condition CTL=5V, EN1=EN2=0V Vo1=5V CTL=0V
CTL=0V
EN=3V
IREG1=1mA IREG2=0mA VIN=5.5 to 25V IREG1=0 to 30mA
IREG2=1mA IREG1=0mA VIN=5.5 to 25V IREG2=0 to 30mA
Vo1: Sweep up
REG1: Sweep up REG1, Sweep down
FB1=REF
FB2=REF
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Electrical characteristics - Continued (unless otherwise noted, Ta=25 VIN=12V, CTL=OPEN, EN1=EN2=5V, FS1=FS2=51k) Standard Value Parameter [H3REG block] Ontime1 Ontime2 Maximum On time 1 Maximum On time 2 Minimum Off time [FET driver block] HG higher side ON resistor HG lower side ON resistor LG higher side ON resistor LG lower side ON resistor [Over voltage protection block] OVP threshold voltage OVP Hysteresis [Short circuit protection block] SCP threshold voltage Delay time [Current limit protection block] Offset voltage [Power good block] Power good low threshold Power good low voltage Delay time Power good leakage current [Soft start block] Charge current Standby voltage [Mode control block] MCTL Low voltage MCTL High voltage MCTL bias current VMCTL_L VMCTL_H IMCTL -0.3 2.3 8 16 0.3 REG1 +0.3 24 V V A ISS VSS_STB 1.5 2.3 3.1 50 A mV VPGTHL VPGL TPGOOD ILEAKPG 0.525 (-25%) 0.4 -2 0.595 (-15%) 0.1 0.75 0 0.665 (-5%) 0.2 1.5 2 V V ms A dVSMAX 80 100 120 mV VSCP TSCP 0.42 (-40%) 0.4 0.49 (-30%) 0.75 0.56 (-20%) 1.5 V ms VOVP dV_OVP 0.77 (+10%) 50 0.84 (+20%) 150 0.91 (+30%) 300 V mV HGHON HGLON LGHON LGLON 3.0 2.0 2.0 0.5 6.0 4.0 4.0 1.0 TON1 TON2 TONMAX1 TONMAX2 TOFFMIN 0.760 0.470 2.5 1.65 0.910 0.620 5 3.3 0.2 1.060 0.770 10 6.6 0.4 s s s s s Symbol MIN. TYP. MAX. Unit
Technical Note
Condition
Vo1=5V Vo2=3.3V Vo1=5V Vo2=33V
ILIM=100k
IPGOOD=1mA
VPGOOD=5V
MCTL=5V
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Output condition table Input EN1 Low Low High High Low Low High High Output REG2(3.3V) DC/DC1 OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF ON ON ON ON
Technical Note
CTL Low Low Low Low High High High High
EN2 Low High Low High Low High Low High
REG1(5V) OFF OFF OFF OFF ON ON ON ON
DC/DC2 OFF OFF OFF OFF OFF ON OFF ON
CTL pin is connected to VIN pin with 1M resistor(pull up) internal IC. EN pin is connected to AGND pin with 1M resistor(pull down) internal IC.
Block Diagram, Application circuit
Vo2 Adjustable Vo1 Adjustable
BOOT2
VIN
BOOT1
VIN
PGND2
3
2
1
31
REG1
32
REG1
22
23
24
26
PGND1 25
SW2
SW1
HG2
HG1
LG2
REG1
REG1
LG1
AGND Short through Protection Circuit SLLMTM Block
CL1 SCP1 OVP1
CL2 SCP2 OVP2
13
Short through Protection Circuit SLLMTM Block
FS2 10
Short Circuit Protect SCP2 REG1 MCTL MCTL
FS1 15
SCP1
RFS1
Short Circuit Protect
5 PGOOD2
20 PGOOD1
Power Good
Over Voltage Protect OVP2
Timer
Timer
Timer
Power Good
FS2
FS1
EN2
TSD
EN1
FB2
REF
UVLO
Timer
H3RegTM Controller Block
H3RegTM Controller Block
Over Voltage Protect OVP1
FB1
REF Thermal Protection
11 6 SS2
Over Current Protect CL2
14 REF 12 SS1 19
Over Current Protect CL1
ILIM2
REF
ILIM1 17
PGND1 SW1
8
SW2 PGND2
MCTL
EN2 4
Vo1
5V Reg
3.3V Reg
SLLM Mode Control
Reference Block
REG1
EN1 21
MCTL1
MCTL2
Vo2
VIN
CTL
REG1
1uF
5.528V
REG1
VIN
REG2
REG2
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3.3V
5V
Vo1
7
9
30
29
28
18
16
27
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REG1
BD9528MUV
Pin Configuration
PGOOD1 BOOT1 MCTL1 ILIM1 SW1 HG1 EN1 SS1
Technical Note
24 PGND1 LG1 Vo1 REG2 REG1 VIN LG2 PGND2 25 26 27 28 29 30 31 32 1 SW2
23
22
21
20
19
18
17 16 15 14 MCTL2 FS1 FB1 AGND
Input MCTL1 Low Low High High MCTL2 Low High Low High
Control Mode SLLM QLLM Forced Continuous Mode Forced Continuous Mode
FIN
13
12 REF 11 10 9 2 HG2 3 BOOT2 4 EN2 5 PGOOD2 6 SS2 7 Vo2 8 ILIM2 FB2 FS2 CTL
MCTL pin is connected to AGND pin with 500k resistor ( pull down) internal IC
Pin Function Table PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 reverse PIN name SW2 HG2 BOOT2 EN2 PGOOD2 SS2 Vo2 ILIM2 CTL FS2 FB2 REF AGND FB1 FS1 MCTL2 ILIM1 MCTL1 SS1 PGOOD1 EN1 BOOT1 HG1 SW1 PGND1 LG1 Vo1 REG2 REG1 VIN LG2 PGND2 FIN PIN Function Highside FET source pin 2 Highside FET gate drive pin 2 HG Driver power supply pin 2 Vo2 ON/OFF pin (High=ON, Low,OPEN=OFF) Vo2 Power Good Open Drain Output pin Vo2 Soft start pin Vo2 Output voltage sense pin OCP setting pin 2 Linear regulator ON/OFF pin (High,OPEN=ON, Low=OFF) Input pin for setting Vo2 frequency Vo2 output voltage feedback pin Output voltage setting pin Input pin Ground Vo1 output voltage feedback pin Input pin for setting Vo1 frequency Mode switch pin 2 ( OPEN = L ) OCP setting pin 1 Mode switch pin 1 ( OPEN = L ) Vo1 Soft start pin Vo1 Power Good Open Drain Output pin Vo1 ON/OFF pin (High=ON, Low,OPEN=OFF) HG Driver power supply pin Highside FET gate drive pin 1 Highside FET source pin 1 Lowside FET source pin 1 Lowside FET gate drive pin 1 Vo1 Output voltage sense pin 3.3V Linear regulator output pin 5V Linear regulator output pin Power supply input pin Lowside FET gate drive pin 2 Lowside FET source pin 2 Exposed Pad1, connect to GND
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Electrical characteristic curves (Reference data)
Technical Note
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
LG 5V/div
LG 5V/div
2us Fig.1 Switching Waveform (Vo=5V, PWM, Io=0A)
2us Fig.2 Switching Waveform (Vo=5V, PWM, Io=8A)
10us Fig.3 Switching Waveform (Vo=5V, QLLM, Io=0A)
LG 5V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
10us Fig.4 Switching Waveform (Vo=5V, SLLM, Io=0A)
LG 5V/div
2us Fig.5 Switching Waveform (Vo=3.3V, PWM, Io=0A)
LG 5V/div
2us Fig.6 Switching Waveform (Vo=3.3V, PWM, Io=8A)
LG 5V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
10us Fig.7 Switching Waveform (Vo=3.3V, QLLM, Io=0A)
LG 5V/div
10us Fig.8 Switching Waveform (Vo=3.3V, SLLM, Io=0A)
LG 5V/div
2us Fig.9 Switching Waveform (Vo=1V, PWM, Io=0A)
LG 5V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
HG 10V/div SW 10V/div
2us Fig.10 Switching Waveform (Vo=1V, PWM, Io=8A)
LG 5V/div
10us Fig.11 Switching Waveform (Vo=1V, QLLM, Io=0A)
LG 5V/div
10us Fig.12 Switching Waveform (Vo=1V, SLLM, Io=0A)
LG 5V/div
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Electrical characteristic curves (Reference data) - Continued
100 80 60 40 20 0 1 10 100 Io[mA] 1000 10000
Technical Note
100 80
100 80
7V
[%]
[%]
7V 12V
21V
40 20 0 1 10
21V
[%]
7V
12V
60
12V
60 40 20 0 1 10
21V
100 Io[mA]
1000
10000
100 Io[mA]
1000
10000
Fig.13 Efficiency (Vo=5V, PWM)
Fig.14 Efficiency (Vo=5V, QLLM)
Fig.15 Efficiency (Vo=5V, SLLM)
100
100
100 80
5V
80
80
7V
60 [%] 40 20 0 1 10 100 Io[mA]
7V 12V
[%]
12V
[%] 60 40 20 0
7V
60
12V
40 20 0
21V
21V
21V
1000
10000
1
10
100 Io[mA]
1000
10000
1
10
100 Io[mA]
1000
10000
Fig.16 Efficiency (Vo=3.3V, PWM)
Fig.17 Efficiency (Vo=3.3V, QLLM)
Fig.18 Efficiency (Vo=3.3V, SLLM)
100 80 60 [%] 40 20 0 1 10 100 Io[mA] 1000 10000
100
100
7V 12V 21V
[%]
80 60 40 20 0 1
7V 12V 21V
[%]
80 60 40 20 0
7V
12V 21V
10
100 Io[mA]
1000
10000
1
10
100 Io[mA]
1000
10000
Fig.19 Efficiency (Vo=1V, PWM) 20us
Vo 100mV/div
Fig.20 Efficiency (Vo=1V, QLLM) 20us
Vo 100mV/div
Fig.21 Efficiency (Vo=1V, SLLM) 20us
Vo 100mV/div
IL 5A/div Io 5A/div
IL 5A/div Io 5A/div
IL 5A/div Io 5A/div
Fig.22 Transient Response (Vo=5V, PWM, Io=08A)
Fig.23 Transient Response (Vo=5V, PWM, Io=80A)
Fig.24 Transient Response (Vo=3.3V, PWM, Io=08A)
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Electrical characteristic curves (Reference data) - Continued 20us
Vo 100mV/div
Technical Note
20us
Vo 100mV/div
20us
Vo 100mV/div
IL 5A/div Io 5A/div
IL 5A/div Io 5A/div
Fig.25 Transient Response (Vo=3.3V, PWM, Io=80A)
Fig.26 Transient Response (Vo=1V, PWM, Io=08A)
Fig.27 Transient Response (Vo=1V, PWM, Io=80A)
IL 5A/div Io 5A/div
Vo 50mV/div
Vo 50mV/div
Vo 50mV/div
2us Fig.28 Output Voltage (Vo=5V, PWM, Io=0A)
2us Fig.29 Output Voltage (Vo=5V, PWM, Io=8A)
10us Fig.30 Output Voltage (Vo=5V, QLLM, Io=0A)
Vo 50mV/div
Vo 50mV/div
Vo 50mV/div
2us Fig.31 Output Voltage (Vo=5V, SLLM, Io=0A)
2us Fig.32 Output Voltage (Vo=3.3V, PWM, Io=0A)
2us Fig.33 Output Voltage (Vo=3.3V, PWM, Io=8A)
Vo 50mV/div
Vo 50mV/div
Vo 50mV/div
10us Fig.34 Output Voltage (Vo=3.3V, QLLM, Io=0A)
2us Fig.35 Output Voltage (Vo=3.3V, SLLM, Io=0A)
2us Fig.36 Output Voltage (Vo=1V, PWM, Io=0A)
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Electrical characteristic curves (Reference data) - Continued
Technical Note
Vo 50mV/div
Vo 50mV/div
Vo 50mV/div
2us Fig.37 Output Voltage (Vo=1V, PWM, Io=8A)
10us Fig.38 Output Voltage (Vo=1V, QLLM, Io=0A)
2us Fig.39 Output Voltage (Vo=1V, SLLM, Io=0A)
EN1 5V/div Vo1 2V/div EN2 5V/div Vo2 2V/div
EN1 5V/div Vo1 2V/div EN2 5V/div Vo2 2V/div
EN1 5V/div Vo1 2V/div EN2 5V/div Vo2 2V/div
Fig.40 Wake up waveform (EN1=EN2)
Fig.41 Wake up waveform (EN2EN1)
Fig.42Wake up waveform (EN1EN2)
IOUT-frequency (VOUT=5V, R(FS)=68k)
IOUT-frequency (VOUT=5V, R(FS)=68k) 500
EN1 5V/div
frequency [kHz]
500
400 VIN=7.5V VIN=12V VIN=18V
frequency [kHz]
PGOOD1 2V/div EN2 5V/div PGOOD2 2V/div
450
450
400 VIN=7.5V VIN=12V VIN=18V
350
350
300 0 1 2 3 4 5 6 7 IOUT [A]
300 0 1 2 3 4 5 6 7 IOUT [A]
Fig.43Wake up waveform (EN1/2PGOOD1/2)
Fig.44 Io-frequency (Vo=5V, PWM, RFS=68k)
Fig.45 Io-frequency (Vo=3.3V, PWM, RFS=68k)
2.5 VOUT=5V VOUT=3.3V
700 600 VOUT=5V 500 frequency [kHz] 400 300 200 VOUT=3.3V
VOUT [V]
5.500 5.000
2 ONTIME [usec]
4.500 4.000 3.500 3.000 2.500 2.000 1.500 1.000 0.500
VIN=7.5V(-5 VIN=21V-5 VIN=7.5V(75 VIN=21V75
1.5
1
0.5
100
0 0 50 RFS [k] 100 150
0 0 50 RFS [k] 100 150
0.000 0 2 4 6 8 IOUT [A] 10 12 14 16
Fig.46 FS-ONTIME
Fig.47 FS-frequency
Fig.48 Ta-IOCP (Vo=5V)
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Electrical characteristic curves (Reference data) - Continued
IOUT - REG1 voltage
3.500
Technical Note
IOUT - REG2 voltage 3.4 3.3 REG2 voltage [V] 3.2 3.1 3 2.9 2.8
5.1 5
VIN=7.5V(-5
3.000
REG1 voltage [V]
2.500
VIN=21V-5 VIN=7.5V(75 VIN=21V75
4.9 4.8 4.7 4.6
VOUT [V]
2.000
1.500
1.000
0.500
4.5
0.000 0 2 4 6 8 IOUT [A] 10 12 14 16
0
50
100
150
200
250
0
50
100
150
200
250
IOUT [mA]
IOUT [mA]
Fig.49 Ta-IOCP (Vo=3.3V)
Fig.50 IREG1-REG1
Fig.51 IREG2-REG2
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Pin Descriptions
Technical Note
VIN (30 pin) This is the main power supply pin. The input supply voltage range is 5.5V to 25V. The duty cycle of BD9528MUV is determined by input voltage and control output voltage. Therefore, when VIN voltage fluctuated, the output voltage also becomes unstable. Since VIN line is also the input voltage of switching regulator, stability depends on the impedance of the voltage supply. It is recommended to establish bypass capacitor and CR filter suitable for the actual application. CTL (9 pin) When CTL pin voltage is at least 2.3V, the status of the linear regulator output becomes active (REG1=5V, REG2=3.3V). Conversely, the status switches off when CTL pin voltage goes lower than 0.8V. The switching regulator doesn't become active when the status of CTL pin is low, if the status of EN pin is high. (CTL pin is connected to VIN pin with 1M resistor(pull up) internal IC) EN1, 2 (21 pin, 4 pin) When EN pin voltage is at least 2.3V, the status of the switching regulator becomes active. Conversely, the status switches off when EN pin voltage goes lower than 0.8V. (EN pin is connected to AGND pin with 1M resistor(pull down) internal IC) REG1 (29 pin) This is the output pin for 5V linear regulator and also active in power supply for driver and control circuit of the inside. The standby function for REG1 is determined by CTL pin. The voltage is 5V, with 100mA current ability. It is recommended that a 10F capacitor (X5R or X7R) be established between REG1 and GND. REG2 (28 pin) This is the output pin for 3.3V linear regulator. The standby function for REG2 is determined by CTL. The voltage is 3.3V, with 50mA current ability. It is recommended that a 10F capacitor (X5R or X7R) be established between REG2 and GND. REF (12 pin) This is the setting pin for output voltage of switching regulator. This IC controls the voltage in the status of REFFB. FB 1, 2 (14 pin, 11 pin) This is the feedback pin from the output of switching regulator. This IC controls the voltage in the status of REFFB. Vo1 (27 pin) This is the output discharge pin, and output voltage feedback pin for frequency setting. When the voltage is beyond 4.4V from the external power supply during operation, it supplies REG1. Vo2 (7 pin) This is the output discharge pin, and output voltage feedback pin for frequency setting. SS1, 2 (19 pin, 6 pin) This is the setting pin for soft start. The rising time is determined by the capacitor connected between SS and GND, and the fixed current inside IC after it is the status of low in standby mode. It controls the output voltage till SS voltage catch up the REF pin to become the SS terminal voltage. FS1, 2 (15 pin, 10 pin) This is the input pin for setting the frequency. It is available to set it in frequency range is 200KHz to 500kHz. ILIM1, 2 (17 pin, 8 pin) BD9528MUV detects voltage differential between SW and PGND, and set OCP. OCP setting current value is determined by the resistance value of ILIM pin. FET of various Ron is available. PGOOD 1, 2 (20 pin, 5 pin) This is the open drain pin for deciding the output of switching regulator. MCTL1, 2 (18 pin, 16 pin) This is the switching shift pin for SLLM (Simple Light Load Mode). MCTL pin is at low level when it goes lower than 0.8V, and at high level when it goes higher than 2.3V. (MCTL pin is connected to AGND pin with 500k resistor(pull down) internal IC) AGND (13 pin) This is the ground pin.
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Technical Note
BOOT1, 2 (22 pin, 3 pin) This is the power supply pin for high side FET driver. The maximum voltage range to GND pin is to 35V, to SW pin is to 7V. In switching operations, the voltage swings from (VIN+REG1) to REG1 by BOOT pin operation. HG1, 2 (23 pin, 2 pin) This is the highside FET gate drive pin. It is operated in switching between BOOT to SW. In case the output MOS is 3ohm /the status of Hi, 2ohm/the status of Low, it is operated hi-side FET gate in high speed. SW1, 2 (24 pin, 1 pin) This is the ground pin for high side FET drive. The maximum voltage range to GND pin is to 30V. Switching operation swings from the status of BOOT to the status of GND. LG1, 2 (26 pin, 31 pin) This is the lowside FET gate drive pin. It is operated in switching between REG1 to PGND. In case the output MOS is 2ohm /the status of Hi, 0.5ohm/the status of Low, it is operated low-side FET gate in high speed. PGND1, 2 (25 pin, 32 pin) This is the ground pin for low side FET drive.
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Technical Note
Explanation of Operation 3 The BD9528MUV is a 2ch synchronous buck regulator controller incorporating ROHM's proprietary H REG CONTROLLA control system. Because controlling of output voltage by a comparator, high response is realized with not relying on the switching frequency. And, when VOUT drops due to a rapid load change, the system quickly restores VOUT by extending the TON time interval. Thus, it serves to improve the regulator's transient response. Activating the Light Load Mode will also exercise Simple Light Load Mode (SLLM) control when the load is light, to further increase efficiency. H3RegTM control
Comparator for output voltage control FB Vout/Vin Circuit VIN
HG SW LG VOU T
A B
Driver
Internal reference voltage REF
Transient Circuit
(Normal operation) FB REF
HG
When FB falls to a reference voltage (REF), the drop is detected, activating the H3REG CONTROLLA system. tON= VOUT x 1 [sec](1) VIN f HG output is determined by the formula above. After the status of HG is OFF, LG go on outputting until output voltage become FB=REF.
LG
(VOUT drops due to a rapid load change) FB REF Io HG LG tON + When VOUT drops due to a rapid load change, and the voltage remains below reference voltage after the programmed tON time interval has elapsed (Output of a comparator for output voltage control =H), the system quickly restores VOUT by extending the tON time, improving the transient response. After VOUT restores (FB=REF), HG turns to be OFF, and it goes back to a normal operation.
(when VIN drops)
VIN
tON1 tON2 tON3 tON4 H3RegTM tON4+
HG
tOFF1 tOFF2 tOFF3 tOFF4=tOFF3 tOFF4=tOFF3
LG FB REF
Output voltage drops FB=REF
If VIN voltage drops because of the battery voltage fall, ontime tON and offtime tOFF is determined by the following formula: tON=VOUT/VINxI/f and tOFF=(VIN-VOUT)/VINxf so that tON lengthen and tOFF shorten to keep output voltage constant. However, if VIN still drops and tOFF equals to tminoff (tminoffMinimum OFF time, regulated inside IC) , because tOFF cannot shorten any 3 TM more, as a result output voltage drops. In H Reg system, lengthening tON time than regulated tON (lengthen tON time until FBREF)
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14/33
2010.03 - Rev.A
BD9528MUV
Technical Note
enables to operate stable not to drop the output voltage even if VIN turns to be low. With the reason above, it is suitable for 2-cell battery. Light Load Control (SLLM) FB REF HG In SLLM, when the status of LG is OFF and the coil current is within 0A (it flows to SW from VOUT.), SLLM function is operated to prevent output next HG. The status of HG is ON, when FB falls below reference voltage again.
LG 0A
(QLLM) REF
HG
FB In QLLM, when the status of LG is OFF and the coil current is within 0A (it flows to SW from VOUT.), QLLM function is operated to prevent output next HG. Then, FB falls below the output programmed voltage within the programmed time (typ=40s), the status of HG is ON. In case FB doesn't fall in the programmed time, the status of LG is ON forcedly and VOUT falls. As a result, he status of next HG is ON.
LG 0A
MCTL1 L L H
MCTL2 L H X
Control mode SLLM QLLM PWM
Running PWM PWM PWM
The BD9528MUV operates in PWM mode until SS pin reaches cramp voltage (2.5V), regardless of the control mode setting, in order to operate stable during the operation. .
Attention: H Reg CONTROLLA monitors the supplying current from capacitor to load, using the ESR of output capacitor, and realize the rapid response. Bypass capacitor used at each load (Ex. Ceramic capacitor) exercises the effect with connecting to each load side. Do not put a ceramic capacitor on COUT side of power supply.
3
TM
COUT
Load
Timing Chart * Soft Start Function EN TSS SS
Soft start is exercised with the EN pin set high. Current control takes effect at startup, enabling a moderate output voltage "ramping start." Soft start timing and incoming current are calculated with formulas (2) and (3) below. Soft start time Tss= REFxCss [sec] (2) 2.3A(typ)
VOUT
Incoming current IIN IIN= CoxVOUT Tss [A] (3)
(Css: Soft start capacitor; Co: Output capacitor)
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15/33
2010.03 - Rev.A
BD9528MUV
Technical Note
Notes when waking up with CTL pin or VIN pin If EN pin is High or short (or pull up resistor) to REG1 pin, IC starts up by switching CTL pin, the IC might fail to start up (SCP function) with the reason below, please be careful of SS pin and REF pin capacitor capacity.
REG1 REG2
VIN
FB
CTL
Inner reference circuit
BG SCP circuit Delay SCP
REF SCP_REF 1ms(typ.)
SCP
SS
PWM
(Switching control signal)
CTL (VIN)
REG1 REG2
REG1, REG2
REG1 UVLO cancellation
BG
0.49V(typ)
SCP_REF
(REF start-up timeSS start-up time) SCP function masked SCP mask cancellation
REF
SS FB
FB starts up as SS reference
SS FB
(REF start-up timeSS start-up time)
REF FB SS
SCP mask
SCP mask cancellation
FB starts up as REF reference After the end of SS wake-up, within SCP delay time (1ms), if REF voltage does not reach SCP_REF(0.49V), SCP turns ON and shut down.
SCP function is masked until SS pin reaches cramp voltage (2.5V).
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2010.03 - Rev.A
BD9528MUV
Output Discharge
Technical Note
VIN,CTL EN
It will be available to use if connecting VOUT pin to DC/DC output. (Total about 100) . Discharge function operates when EN='L' UVLO=ON(If input voltage is low) SCP Latch time TSD=ON. The function at output discharge time is shown as left. (1)during EN='H'`L' If EN pin voltage is below than EN threshold voltage, output discharge function is operated, and discharge output capacitor charge.
VOUT
VIN, CTL REG1
VOUT
The efficiency of VIN voltage drop Output Discharge
Output Hi-Z UVLO ON
(2) during VIIN=CTL=H0V IC is in normal operation until REG1 voltage becomes lower than UVLO voltage. However, because VIN voltage also becomes low, output voltage will drop, too. If REG1 voltage reaches the UVLO voltage, output discharge function is operated, and discharge output capacitor charge. In addition, if REG1 voltage drops, inner IC logic cannot operate, so that output discharge function does not work, and becomes output Hi-z. In case, FB has resistor against GND, discharge at the resistor.
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17/33
2010.03 - Rev.A
BD9528MUV
Technical Note
Timer Latch Type Short Circuit Protection FB REFx0.7 Short protection kicks in when output falls to or below REF X 0.7. When the programmed time period elapses, output is latched OFF to prevent destruction of the IC. (HG=Low, LG=Low) Output voltage can be restored either by reconnecting the EN pin or disabling UVLO.
SCP
1ms(typ)
EN / UVLO Over Voltage Protection FB REFx1.2 When output rise to or above REFx1.2 (typ), output over voltage protection is exercised, and low side FET goes up maximum for reducing output.(LG=High, HG=Low).When output falls, output voltage can be restored., and go back to the normal operation.
HG
LG
Switching Over current protection circuit
tON HG
tON
tON
tON
LG
During the normal operation, when FB becomes less than REF, HG becomes High during the time tON, and after HG becomes OFF, it output LG. However, when inductor current exceeds ILIMIT threshold, next HG pulse doesn't pulsate until it is lower than ILIMIT level.
IL
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18/33
2010.03 - Rev.A
BD9528MUV
External Component Selection 1. Inductor (L) selection
Technical Note
IL
VIN
IL VOUT L Co
The inductor value is a major influence on the output ripple current. As formula (4) below indicates, the greater the inductor or the switching frequency, the lower the ripple current. (VIN-VOUT)xVOUT [A](4) IL= LxVINxf The proper output ripple current setting is about 30% of maximum output current. IL=0.3xIOUTmax. [A](5) (VIN-VOUT)xVOUT L= ILxVINxf [H](6)
(IL: output ripple current; f: switch frequency) Output ripple current Passing a current larger than the inductor's rated current will cause magnetic saturation in the inductor and decrease system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor rated current value. To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance. 2.Output Capacitor (CO) Selection
VIN
VOUT L ESR Co
When determining the proper output capacitor, be sure to factor in the equivalent series resistance required to smooth out ripple volume and maintain a stable output voltage range. Output ripple voltage is determined as in formula (7) below. VOUT=ILxESR+ESLxIL/TON(7) (IL: Output ripple current; ESR: CO equivalent series resistance) In selecting a capacitor, make sure the capacitor rating allows sufficient margin relative to output voltage. Note that a lower ESR can minimize output ripple voltage.
Output Capacitor
Please give due consideration to the conditions in formula (8) below for output capacity, bear in mind that output rise time must be established within the soft start time frame. Capacitor for bypass capacitor is connected to Load side which connect to output in output capacitor capacity (CEXT, figure above). Please set the soft start time or over current detecting value, regarding these capacities. Co Tssx(Limit-IOUT) VOUT (8) Tss: Soft start time Limit: Over current detection
Note: Improper capacitor may cause startup malfunctions. 3. Input Capacitor (Cin) Selection
VIN Cin
The input capacitor selected must have low enough ESR resistance to fully support large ripple output, in order to prevent extreme over current. The formula for ripple current IRMS is given in (9) below.
VOUT
VIN(VIN-VOUT) IRMS=IOUTx VIN [A](9) IOUT Where VIN=2xVOUT, IRMS= 2
L
Co
Input Capacitor A low ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
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2010.03 - Rev.A
BD9528MUV
4. MOSFET Selection
Technical Note
MOSFET may cause the loss as below, so please select proper FET for each.
VIN main switch
Loss on the main MOSFET Pmain=PRON+PGATE+PTRAN =
VOUT
VOUT VIN
xRONxIOUT2+CissxfxVDD+
2 VIN xCrssxIOUTxf IDRIVE
(10)
L Co
(Ron: On-resistance of FET; Ciss: FET gate capacitance; f: Switching frequency Crss: FET inverse transfer function; IDRIVE: Gate peak current) Loss on the synchronous MOSFET Psyn=PRON+PGATE = VIN-VOUT VIN xRONxIOUT2+CissxfxVDD (11)
synchronous switch
5. Setting output voltage This IC is operated that output voltage is REFFB. And it is operated that output voltage is feed back to FB pin.
R2 V OUT I Ripple ESR V OUT (R1 R2) REF(0.7V)
(VOUT:Output ripple voltage) V OUT (Iripple: ripple current of coil, ESR: ESR of output capacitor) 2 (L:inductance[H] f:switching frequency[Hz])
1
I Ripple (V IN V OUT )
V OUT (L V IN f)
(Notice)
Please set VOUT more than 20mV
Ex. VIN=20V,VOUT=5V,f=300kHz,L=2.5uH,ESR=20m,R1=56K,R2=9.1k -6 3 Iripple=(20V-5V)x5V/(2.5x10 Hx20Vx300x10 Hz)=5[A] -3 VOUT=5Ax20x10 =0.1[V] VOUT=(51k+9.1k)/9.1k+1/2x0.1V=5.057[V] Select (R1 + R2) under 100K(recommend)
VIN
VIN
H3REG CONTROLLA
R S
Q
SLLM Driver SLLM Circuit Output voltage
FB VIN R1 R2
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20/33
2010.03 - Rev.A
BD9528MUV
6. Setting over current protection VIN
Technical Note
L VOUT
SW
Co
PGND
Detecting the ON resistance (between SW and PGND voltage) of MOSFET at low side, it set the over current voltage protection. Over current reference voltage (ILIM_ref) is determined as in formula(12) below. 10x103 ILIM_REF = RILIM[K]xRON[m] [A](12)
RILIM
(RILIM: Resistance for setting of over current voltage protection value[k] RON: Low side ON resistance value of FET[m]) However, the value, which set the over current protection actually, is determined by the formula (13) below. 1 IL Iocp= ILIM_ref + 2 1 I x Vo (13) x VIN - Vo x = ILIM_ref + VIN f 2 L (ILCoil ripple current[A], VINInput voltage[V], VoOutput voltage[V] Switching frequency[HZ], LCoil inductance[H])
Coil current
Iocp ILIM_ref
(Example) If load current 5A want to be realized with VIN=619V, VOUT=5V, =400kHZ, L=2.5uH, RON=20m, the formula would be below. 10k 1 I x Vo 5 x VIN - Vo x + Iocp= RILIM[k] xRON[m] VIN 2 f L When VIN=6V, Iocp will be minimum(this is because the ripple current is also minimum) so that if each condition is input, the formula will be the following: RILIM109.1[k]. To design the actual board, please consider enough margin for FET ON resistor dispersion, Coil inductor dispersion, IC over current reference value dispersion, frequency dispersion. 7. Relation between output voltage and TON time The BD9528MUV, both 1ch and 2ch, are high efficiency synchronous regulator controller with frequency variable. TON time varies with Input voltage [VIN], output voltage [VOUT], and RFS of FS pin resistance. TON time is calculated with the following formula: VOUTRFS TON =k VIN From TON time above, frequency on application condition is following: [kHz](15) VIN Ton However, real-life considerations (such as the external MOSFET gate capacitor and switching speed) must be factored in as they affect the overall switching rise and fall time, so please confirm in reality by the instrument. Frequency = VOUT x 1 [nsec](14)
3.5 3 2.5 ontime[us] 2 1.5 1 0.5 0 0 20 40 60 RFS[k] 80 100 120
VIN=7V VIN=12V VIN=21V
2.5
VIN=7V
1 0.9 0.8 0.7 ontime[us] 0.6 0.5 0.4 0.3 0.2 0.1 0 0 20 40 60 RFS[k] 80 100 120 0 20 40 60 RFS[k] 80 100 120
VIN=7V VIN=12V VIN=21V VIN=12V VIN=21V
2 ontime[us] 1.5 1 0.5 0
RFS - ontime(VOUT=5V)
RFS - ontime(VOUT=3.3V)
RFS - ontime(VOUT=1V)
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21/33
2010.03 - Rev.A
BD9528MUV
Technical Note
8. Relation between output voltage and frequency Because the BD9528MUV is TON time focused regulator controller, if output current is up, switching loss of Coil, MOSFET and output capacitor will increase, and frequency will be fast. Loss of each Coil, MOSFET and output capacitor are below. Coil loss
2 = IOUT x DCR
VOUT MOSFET(High Side) loss MOSFET(Low Side) loss = IOUT x Ronh x = IOUT x Ronl x (12 2
VIN VOUT VIN
)
(Ronh : ON resistance of high side MOSFET, Ronl : ON resistance of low side MOSFET, ESR : Output capacitor equivalent cascade resistance)
Regarding those loss above and frequency formula, it is determined below. VIN x IOUT x TON VOUT x IOUT + + + However, real-life considerations (such as parasitic resistance element of Layout pattern) must be factored in as they affect the loss, please confirm in reality by the instrument.
T (=1/Freq) =
(16)
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22/33
2010.03 - Rev.A
BD9528MUV
I/O Equivalent Circuit
Technical Note
1, 24pin (SW2, SW1)
BOOT
2, 23pin (HG2, HG1)
BOOT HG BOOT
3, 22pin (BOOT2, BOOT1)
HG SW SW
4, 21pin (EN2, EN1)
5, 20pin (PGOOD2, PGOOD1)
6, 19pin (SS2, SS1)
REG1
12pin (REF)
REG1
11, 14pin (FB2, FB1)
10, 15pin (FS2, FS1)
16, 18pin (MCTL2, MCTL1)
9pin (CTL)
VIN
26, 31pin (LG1, LG2)
REG1
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23/33
2010.03 - Rev.A
BD9528MUV
I/O Equivalent Circuit 7, 27pin (Vo2, Vo1) 28pin (REG2)
REG1 VIN
Technical Note
29pin (REG1)
VIN
30pin (VIN)
8, 17pin (ILIM2, ILIM1)
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24/33
2010.03 - Rev.A
BD9528MUV
Evaluation Board Circuit (Vo1=5V/8A f1=300kHz Vo2=3.3V/8A f2=300kHz)
VIN 7V28V R1 30 VIN CTL REG1 EN1 REG1 EN2 R4 4 REG1 5V C2 REG2 3.3V C3 R18 12 C4 19 R3 21 EN2 R2 9 EN1 CTL C1
Technical Note
BD9528MUV VIN BOOT1 CTL HG1 EN1 EN2 REG1 PGND1
28 25 23 24 22 R9
VIN
VIN
C9 R10 C7 Q2 SW1
C10
VO1 L1 C13 R17 C23 C14 C15 C16 C17
SW1
D1
LG1
26
R11
Q1
29
REG2
FB1
14 C24
REF
Vo1
27 VIN VIN
SS1 BOOT2
3
R12 C8 Q4 C11 SW2 C12 VO2 L2 C18 R14 C19 C20 C21 C22
6 C5 C6
SS2
R13
HG2
17
2
ILIM1
SW2 LG2
1
R5 31 32 11 8 R6 15 R7
Q3
D2
R19
C25
ILIM2
PGND2 FB2
FS1 Vo2
7 REG1 R15 PGOOD1
C26 R20
10 R8
FS2 PGOOD1
20 REG1 PGOOD2
MCTL1
18 R28
MCTL1
R16
PGOOD2
MCTL2 16 R27
5
MCTL2 AGND
13
DESIGNATION R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R27 R28 C1 C2 C3 C4 C5 C6
RATING 0 0 0 68k 68k 75k 75k 0 0 0 0 0 0 100k 100k 91k 15k 30k 8.2k 0 0 10uF(25V) 10uF(6.3V) 10uF(6.3V) 0.1uF(6.3V) 2200pF(50V) 2200pF(50V)
PART No. MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 CM32X7R106M25A GRM21BB10J106KD GRM21BB10J106KD GRM21BB10J104KD GRM188B11H102KD GRM188B11H102KD
COMPANY ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM KYOCERA MURATA MURATA MURATA MURATA MURATA
DESIGNATION C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 L1 L2 Q1 Q2 Q3 Q4 U1
RATING 0.47uF(10V) 0.47uF(10V) 10uF(25V) 10uF(25V) 330uF 330uF Diode Diode 2.5uH 2.5uH FET FET FET FET -
PART No. GRM188B11A474KD GRM188B11A474KD CM32XR7106M25A CM32XR7106M25A 6TPE330MI 6TPE330MI RSX501L-20 RSX501L-20 CDEP105NP-2R5MC-32 CDEP105NP-2R5MC-32 uPA2709 uPA2709 uPA2709 uPA2709 BD9528MUV
COMPANY MURATA MURATA KYOCERA KYOCERA SANYO SANYO ROHM ROHM Sumida Sumida NEC NEC NEC NEC ROHM
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25/33
2010.03 - Rev.A
BD9528MUV
Evaluation Board Circuit for Low input voltage(Vo1=5V/8A f1=300kHz Vo2=3.3V/8A f2=300kHz)
VIN 6V28V R1 30 VIN CTL REG1 EN1 REG1 EN2 R4 4 REG1 5V C2 REG2 3.3V C3 R18 12 C4 19 R3 21 EN2 R2 9 EN1 CTL C1
Technical Note
BD9528MUV VIN BOOT1 CTL HG1 EN1 EN2 REG1 PGND1
28 25 23 24 22 R9
VIN
VIN
C9 R10 C7 Q2 SW1
C10
VO1 L1 C13 R17 C23 C14 C15 C16 C17
SW1
D1
LG1
26
R11
Q1
29
REG2
FB1
14 C24
REF
Vo1
27 VIN VIN
SS1 BOOT2
3
R12 C8 Q4 C11 SW2 C12 VO2 L2 C18 R14 C19 C20 C21 C22
6 C5 C6
SS2
R13
HG2
17
2
ILIM1
SW2 LG2
1
R5 31 32 11 8 R6 15 R7
Q3
D2
R19
C25
ILIM2
PGND2 FB2
FS1 Vo2
7 REG1 R15 PGOOD1
C26 R20
10 R8
FS2 PGOOD1
20 REG1 PGOOD2
MCTL1
18 R28
MCTL1
R16
PGOOD2
MCTL2 16 R27
5
MCTL2 AGND
13
DESIGNATION R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R27 R28 C1 C2 C3 C4 C5 C6
RATING 0 0 0 68k 68k 75k 75k 0 10 10 0 10 10 100k 100k 56k 9.1k 30k 8.2k 0 0 10uF(25V) 10uF(6.3V) 10uF(6.3V) 0.1uF(6.3V) 2200pF(50V) 2200pF(50V)
PART No. MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 MCR03 CM32X7R106M25A GRM21BB10J106KD GRM21BB10J106KD GRM21BB10J104KD GRM188B11H102KD GRM188B11H102KD
COMPANY ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM ROHM KYOCERA MURATA MURATA MURATA MURATA MURATA
DESIGNATION C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 L1 L2 Q1 Q2 Q3 Q4 U1
RATING 0.47uF(10V) 0.47uF(10V) 10uF(25V) 10uF(25V) 330uF 330uF 10pF(50V) Diode Diode 2.5uH 2.5uH FET FET FET FET -
PART No. GRM188B11A474KD GRM188B11A474KD CM32XR7106M25A CM32XR7106M25A 6TPB330ML 6TPE330MI RSX501L-20 RSX501L-20 CDEP105NP-2R5MC-32 CDEP105NP-2R5MC-32 uPA2709 uPA2709 uPA2709 uPA2709 BD9528MUV
COMPANY MURATA MURATA KYOCERA KYOCERA SANYO SANYO ROHM ROHM Sumida Sumida NEC NEC NEC NEC ROHM
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26/33
2010.03 - Rev.A
BD9528MUV
Handling method of unused pin during using only DC/DC 1ch
Technical Note
If using only 1ch DC/DC and 2ch pin is set to be off at all times, please manage the unused pin as diagram below.
PIN No, 1 2 3 4 5 6 7 8 10 11 31
PIN name SW2 HG2 BOOT2 EN2 PGOOD2 SS2 Vo2 ILIM1 FB2 FS2 LG2
Management GND Open Open GND GND GND GND GND GND GND Open
VIN 12V
BD9528MUV
R1 30
VIN
VIN
VIN BOOT1
22
VIN CTL REG1 EN1 R3 R2
CTL
C1 9
R9 C9 C10
CTL HG1
23 24
R10
C7 Q2 SW1 L1 C13 R17 Q1 C23 C14 C15 C16 C17 VO1
EN1 21
EN1 EN2 REG1
SW1
D1 4 REG1 5V C2 REG2 3.3V C3 R18 12 C4 19
LG1 PGND1
26
R11
29
25
28
REG2
FB1
14 C24
REF
Vo1
27
SS1 BOOT2
3
6 C5
SS2 HG2
2
17 R5 8
ILIM1
SW2 LG2
1
ILIM2
PGND2 FB2
32 10
15 R7
FS1 Vo2
7 REG1 R15 PGOOD1
10
FS2 PGOOD1
20
MCTL1 18 R28
MCTL1 PGOOD2
5
MCTL2 16 R27
MCTL2 AGND
13
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27/33
2010.03 - Rev.A
BD9528MUV
Example of PCB layout
Technical Note
L Co
L-FET (CH1)
Vo1

`Silent'GND
High current GND
C
Cin
BOOT1
SS1
SW1
HG1
EN1
PGOOD1
MCTL1
ILMI1
C
Cin
SW2
HG2
EN2
SS2
Vo2
ILIM2
PGND2
PGOOD2
BOOT2
R R
H-FET (CH2)
High current GND
C
L-FET (CH2)
Because high pulse current rush into power loop, consisted of input capacitor Cin, Output inductor L, and Output capacitor Co, this part layout should be built, including GND pattern, at parts side (upper side). Also ,please avoid to draw via formation in power loop line. (The reason is that it will be a factor of noise because via oneself holds some nH parasitic inductance) FB pin has comparatively high impedance, so floating capacity should be minimum as possible. And feedback wiring from output should be taken properly, and put on shield, not going through around L (because of magnetic). Please be careful in drawing) Trace from SW node pin to inductor should be cut short . And both inductor element pattern should be kept away. (Closer wiring has SW node noise influence Vo by parasitic capacity between wiring ). This layout example shows that SW node is outside, but if the application board will be like that , SW node should be shielding, and consider the influence to other circuit. Input capacitor Cin should be placed cloase to IC with low inductance and low impedance . If that is difficult, please place a capacitor for high frequency removal with PKG size small like 0.1uF (ESL small). 2 layer and 3 layer are plain GND, so connect from parts side GND to plain GND by low impedance with many via as possible. Inner GND is only for shielding, so that not to form loop for high current . Please take GND pattern space widely, and design layout to be able to increase radiation efficiency. FS pin nad ILIM pin has high impedance. External resistor should be connected to "Silent GND".
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H-FET (CH1)

R R R R
C
PGND1 LG1 Vo1
MCTL2 FS1 FB1 AGND REF FB2 FS2 CTL
VIN
REG2 REG1 VIN LG2
R

`Silent'GND
C
Co L
Vo2
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BD9528MUV
Technical Note
Input current A
Input current B
Vin DC/DC
H3Reg
controller
SW pin voltage
Inductor current
Vout
Feed back line
GND
Power GND Analog GND
Output current GND Output current GND
Power GND
This part is shortened.
Vin
current Charger current current Current leveled By capacitor Pulsed current flows by ON/OFF of the switch
Cin
t t
Input current A
Input current B
Noise output !! This part is shortened.
SW
Voltage
L
The noise has decreased by LC filter
Vout
current Inductor ripple current
Vin
Cout
Output current t SW pin voltage Inductor current t
0V
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2010.03 - Rev.A
BD9528MUV
Technical Note
The influence of inductor is noted The impedance of the output is low = It may be long
SW
L
Vout
FB
Cout
The impedance of this line is high This distance is shorted as much as possible
The impedance of FB pin is higher
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2010.03 - Rev.A
BD9528MUV
Technical Note
Notes for use 1. This integrated circuit is a monolithic IC, which (as shown in the figure below), has P+ isolation in the P substrate and between the various pins. A P-N junction is formed from this P layer and N layer of each pin, with the type of junction depending on the relation between each potential, as follows: When GND element A element B, the P-N junction is a diode. When element BGND element A, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, as well as operating malfunctions and physical damage. Therefore, be careful to avoid methods by which parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an input pin.
Resistor Pin A Pin A
N N P
+
Transistor (NPN) Pin B
C B E B P P
+
Pin B
N P P
+
N
Parasitic element
P+
N N
C E
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic Other adjacent elements
2. In some modes of operation, power supply voltage and pin voltage are reversed, giving rise to possible internal circuit damage. For example, when the external capacitor is charged, the electric charge can cause a VCC short circuit to the GND. In order to avoid these problems, inserting a VCC series countercurrent prevention diode or bypass diode between the various pins and the VCC is recommended.
Bypass diode Counter current prevention diode
VCC Pin
3. Absolute maximum rating
Although the quality of this IC is rigorously controlled, the IC may be destroyed when applied voltage or operating temperature exceeds its absolute maximum rating. Because short mode or open mode cannot be specified when the IC is destroyed, it is important to take physical safety measures such as fusing if a special mode in excess of absolute rating limits is to be implemented.
4.GND potential Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the operating mode. 5. Thermal design In order to build sufficient margin into the thermal design, give proper consideration to the allowable loss (Power Dissipation) in actual operation. 6. Short-circuits between pins and incorrect mounting position When mounting the IC onto the circuit board, be extremely careful about the orientation and position of the IC. The IC may be destroyed if it is incorrectly positioned for mounting. Do not short-circuit between any output pin and supply pin or ground, or between the output pins themselves. Accidental attachment of small objects on these pins will cause shorts and may damage the IC. 7. Operation in strong electromagnetic fields Use in strong electromagnetic fields may cause malfunctions. Use extreme caution with electromagnetic fields.
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2010.03 - Rev.A
BD9528MUV
Technical Note
8. Thermal shutdown circuit This IC is provided with a built-in thermal shutdown (TSD) circuit, which is activated when the operating temperature reaches 175 (standard value), and has a hysteresis range of -15 (standard value). When the IC chip temperature rises to the threshold, all the inputs automatically turn OFF. Note that the TSD circuit is provided for the exclusive purpose shutting down the IC in the presence of extreme heat, and is not designed to protect the IC per se or guarantee performance when or after extreme heat conditions occur. Therefore, do not operate the IC with the expectation of continued use or subsequent operation once the TSD is activated. 9. Capacitor between output and GND When a larger capacitor is connected between the output and GND, Vcc or VIN shorted with the GND or 0V line - for any reason - may cause the charged capacitor current to flow to the output, possibly destroying the IC. Do not connect a capacitor larger than 1000uF between the output and GND. 10. Precautions for board inspection Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC. Therefore, be certain to use proper discharge procedure before each process of the operation. To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handling, transfer and storage operations. Before attempting to connect components to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply is OFF before removing any component connected to the test setup. 11. GND wiring pattern When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from the wiring resistance and high current does not cause any voltage change in the small-signal GND. In the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND.
Thermal Derating Curve VQFN032V5050
[mW] 1000
880mW 800
74.2mmx74.2mmx1.6mm j-a=142.0/W
Glass-epoxy PCB
Power Dissipation [Pd]
600
IC Only j-a=328.9/W
400 380mW
200
0
25
50
75
100
125
150
[]
Ambient Temperature [Ta]
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2010.03 - Rev.A
BD9528MUV
Ordering part number
Technical Note
B
D
9
Part No.
5
2
8
M
U
V
-
E
2
Part No.
Package MUV: VQFN032V5050
Packaging and forming specification E2: Embossed tape and reel
VQFN032V5050
5.00.1
5.0 0.1

Tape Quantity Direction of feed Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
1PIN MARK
1.0MAX
S
+0.03 0.02 -0.02 (0.22)
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S C0.2
0.4 0.1
32
3.40.1
1 8 9
25 24 17
16
0.75 0.5
3.4 0.1
+0.05 0.25 -0.04
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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2010.03 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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http://www.rohm.com/contact/
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R1010A

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